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Ultra Secure Four Channel I2C interface

DNx-I2C-534, DNA-I2C-534, DNR-I2C-534, DNF-I2C-534

Features

  • Fully compatible with RACKtangle, FlatRACK and Cube chassis
  • Four independent master/slave channels
  • Fully conforms to UM10204 at SM, FM and FM+ bit rates
  • Guardian read-back of master transmissions confirms validity of transmit data
  • Full data path integrity confirmed with CRC
  • Standard dSub 37 connectivity
  • Includes all software including C source code
  • No royalties or license required
Ultra Secure Four Channel I2C interface
Product Style: What do the "DNx" prefixes mean? "DNA" prefix is for a Cube & MIL Cube Board, "DNR" prefix is for a Rack & MIL Rack Board , and "DNF" prefix is for a FLATRACK board.
Quantity: 2770
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Typically in stock for shipment in 3-4 weeks. Subject to global supply chain challenges.

DNx-I2C-534, DNA-I2C-534, DNR-I2C-534, DNF-I2C-534

The DNR-I2C-534, DNF-I2C-534 and DNA-I2C-534 are four channel I2C interfaces designed for use with UEI’s popular RACKtangle,FlatRACK and Cube chassis respectively. They are fully supportedby both PowerDNA (hosted) and UEIPAC (standalone/embedded)options of the chassis.

The I2C interface is compliant with UM10204 and supports Standard-Mode (100 kbit/s), Fast-Mode (400 kbit/s) and Fast-Mode+ (1Mbit/s), Inputs and outputs are 3.3/5 V compatible and are broughtout through a dSub 37 connector. The DNA-CBL-COM series brings the four I2C ports out to 9-pin dSub connectors.

Each of the four channels has both master and slave capability. TheSCL and SDA pins include 1.5 kOhm pull up resistors to ensure reliable operation.

The standard I2C transaction includes sending a packet and thenreceiving an acknowledge. Failure to receive an ACK is an errorcondition. However, some I2C devices do not respond with an ACK.The DNx-I2C-534 can be set in a mode where it does not wait for anACK, and does not generate an error message if the standard ACKis not received.

The board is part of UEI”s popular Guardian series. The master ofeach channel can be connected to the channels slave port via on-board switches. This allows the system to confirm the correct datahas been sent out from each master.

To ensure data security and reliability from the host PC and/or embedded CPU, a CRC checksum is added to each I2C transaction written. This checksum remains with the data as it moves through thesystem and is checked by the DNx-I2C-534 FPGA prior to it beingwritten to the output drivers. On data reads, the board’s FPGA addsa CRC checksum to the data and this is confirmed by the CPU priorto presenting the data to the application software. Note the FPGAis the last device in the data chain and reads and writes directly tothe I2C receiver/transmitter chip.

The DNx-I2C-534 includes all software required for operation inboth UEIPAC and PowerDNA chassis deployments. There are no license or royalty payments ever required and software revision up-dates are always available on the UEI web site at no charge.

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Compatibility

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